Semiconductor memory device having error correcting circuit and method for correcting error

ABSTRACT

In a semiconductor memory device having an error correcting circuit, a pair of bit lines and inverted bit lines are connected to the inputs of first and second inverting amplitude circuits through a first and second N channel MOS transistors, respectively, and the output of the first inverting amplitude circuit is connected to the bit line through a third transistor and the output of the second inverting amplitude circuit is connected to the inverted bit line through a fourth transistor. When an error of information of any bit line pair is detected by an error detecting circuit, the first and second N channel MOS transistors are turned off and each bit line pair is separated from the input of the first and second inverting amplitude circuits and, as a result, information of a bit line pair is rewritten by the output of the first and second inverting amplitude circuits.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device having anerror correcting circuit and a method for correcting an error. Moreparticularly, the present invention relates to a semiconductor memorydevice having an error correcting circuit for detecting and correctingan error in the information read from each memory cell incorporated in asemiconductor memory device and a method for correcting an error.

2. Description of the Prior Art

FIG. 1 is a schematic block diagram showing a conventional MOS dynamicRAM.

Referring to FIG. 1, a description is made of the whole structure of theconventional MOS dynamic RAM. A row address signal is externally appliedto a row address buffer 1. The row address buffer 1 stores the rowaddress signal and applies the same to a row decoder 2. The row decode 2decodes the row address signal to specify a column address of a memorycell array 3. On the other hand, a column address signal is externallyapplied to a column address buffer 4. The column address buffer 4 storesthe column address signal and applies the same to a column decoder 5.The column decoder 5 decodes and applies the column address signal tothe memory cell array 3 through a sense amplifier 6 to specify a rowaddress of the memory cell array 3.

A sense signal generating circuit 7 and an I/O circuit 9 are connectedto the sense amplifier 6. The sense signal generating circuit 7 outputsa signal for driving the sense amplifier. The input/output of the I/Ocircuit 9 is switched by an output control circuit 8. More specifically,when the I/O circuit 9 is switched to the input side, the inputted datais stored in a predetermined addressed memory cell in the memory cellarray through the sense amplifier 6. When the I/O circuit 9 is switchedto the output side, data is read from a predetermined addressed memorycell and outputted from the sense amplifier 6 through the I/O circuit 9.The memory cell array 3 comprises n×m memory cells.

FIG. 2 is a diagram showing in greater detail a memory cell in the MOSdynamic RAM shown in FIG. 1. Referring to FIG. 2, a description is madeof a memory cell of the conventional MOS dynamic RAM. Memory cells MC₀,₀ to MC₆₃, ₆₃ constitute a memory cell array with 64 rows and 64columns, each of cells being a dynamic type of one-transistorone-capacitance type formed of an N channel MOS transistor Q andcapacitance C_(S). Word lines W₀ to W₆₃ are connected to each of memorycells MC₀, ₀ to MC₆₃, ₆₃ and each of word lines W₀ to W₆₃ is selected bya row decoder 2 in response to a row address signal externally applied.Bit line pairs of the BL₀ and BL₀ to BL₆₃ and BL₆₃ are connected to eachof memory cells MC₀, ₀ to MC₆₃, ₆₃ in a column direction. Dummy wordlines DW₀ and DW₁ are connected to dummy cells DM₀, ₀ to DM₆₃, ₁ and anydummy cell is selected by the dummy word lines DW₀ and DW₁.

Sense amplifiers SA₀ to SA₆₃ including P channel MOS transistors 61 and62 and N channel MOS transistors 63 and 64 connected in a crossingmanner are connected to the bit line pairs BL₀ and BL₀ to BL₆₃ and BL₆₃.Activation signals SP and SN generated from a sense signal generatingcircuit 7 are applied to each source of the P channel MOS transistors 61and 62 and the N channel MOS transistors 63 and 64 comprised in thesense amplifiers SA₀ to SA₆₃.

The bit line pairs BL₀ and BL₀, and BL₆₃ and BL₆₃ are connected to I/Obus line pair I/O and I/O through N channel MOS transistors 10 to 13. Ysignal lines Y₀ to Y₆₃ are applied from the column decoder 5 to thegates of the N channel MOS transistors 10 to 13. Conduction of the Nchannel MOS transistors 10 to 13 between bit line pairs BL₀ and BL₀ toBL₆₃ and BL₆₃ is controlled by the Y signal lines Y₀ to Y₆₃. A dataoutput main amplifier 91 and a data input buffer 92 are connected to theI/O bus line pair I/O and I/O. The data output main amplifier 91 outputsthe information from the I/O bus line pair I/O and I/O as a data outputDO to outside during a reading cycle. The data input buffer 92 convertsthe level of a data input DI externally applied and applies them to theI/O bus line pair I/O and I/O as a complementary signal during a writingcycle.

Next, a description is made of the operation of the memory. During thereading cycle, assuming that, for example, the memory cell MC₀, ₀ isselected, the row decoder 2 raises a potential of the word line W₀ andthe dummy word line DW₀ and an electric charge stored in the storagecapacitance C_(S) is transferred to the bit line pairs BL₀ and BL₀ toBL₆₃ and BL₆₃ which have been previously charged to the same potential.For example, an electric charge representing information of the memorycell MC₀, ₀ is transferred to the bit line BL₀ and an electric charge ofthe dummy cell DM₀, ₀ is transferred to the inverted bit line BL₀ so asto generate a reference voltage.

When the sense amplifier activation signal SN becomes a low level andthe activation signal SP becomes a high level, the sense amplifiers SA₀to SA₆₃ are activated. More specifically, a minute difference of asignal voltage caused by an electric charge representing informationtransferred to the bit line pairs BL₀ and BL₀ to BL₆₃ and BL₆₃ is sensedand amplified. Then, a Y signal line (Y₀ in this case) is selected inresponse to a column address signal which was externally applied to thecolumn decoder 5 and the potential thereof is raised to cause a voltageof a complementary signal on the bit line pair BL₀ and BL₀ to betransferred to the I/O bus line pair I/O and I/O, respectively,amplified by the data output main amplifier 91 and outputted as the dataoutput DO.

During the writing cycle, data is written to a desired memory cellthrough a path opposite to the reading cycle. More specifically, thelevel of the data input signal DI applied from the outside of the chipis converted by the data input buffer 92 and transmitted as acomplementary signal to the I/O bus line pair I/O and I/O. If the Y₀signal line, for example, is selected by the column decoder 5, thecomplementary data input signal on the I/O bus pair I/O and I/O istransferred to the bit line pair BL₀ and BL₀. At this time, if the wordline W₀, for example, has been selected, the information is written inthe memory cell MC₀, ₀ on the intersecting point of the word line W₀ andthe bit line pair BL₀ and BL₀.

Meanwhile, the conventional MOS dynamic RAM was constituted as describedabove, the error detecting and correcting circuit was generallyconnected to the outside. If the error detecting and collecting circuitis contained in the chip, the error detecting and correcting circuit isconnected to the output of the data output main amplifier 91 and theinput of the data input buffer 92. Then, the data read from the memorycell array 3 is applied to the error detecting and correcting circuitthrough the I/O bus line pair I/O and I/O and the data output mainamplifier 91 to detect and correct the error in the data and the errorcorrected data is written into the memory cell array 3 through the datainput buffer 92 and the I/O bus line pair I/O and I/O. However, when theerror is detected and corrected in this way, there is such disadvantagethat it takes time to detect and correct the error in data.

In order to reduce time for detecting and correcting the error, thenumber of data bits useful for detecting the error is to increase at thesame time, but if the bit number is increased, the number of the I/O busline pair I/O and I/O is increased, so that chip area is also increased.

As another example of the MOS type dynamic RAM containing the errorcorrecting circuit, there is "A Submicron 1M bit Dynamic RAM with a4-Bit-at-a-Time Built-In ECC Circuit" IEEE JOURNAL OF SOLID-STATECIRCUITS. Vol. SC-19, No. 5 OCTOBER 1984, which is proposed by Yamada,et al. However, this proposed correcting circuit of the dynamic RAM hasa relatively complicated structure.

SUMMARY OF THE INVENTION

One object of the invention is to provide a semiconductor memory devicehaving improved error correction.

Another object of the invention is to provide error detection andcorrection in a semiconductor memory device without requiring use of theI/O lines therefor.

Another object of the invention is to provide, in a semiconductordevice, method and circuitry for carrying out error correction havingimproved error detection and correction rate.

A further object is to provide error correction in a semiconductordevice wherein the number of bits undergoing correction may be increasedwithout increasing the number of I/O lines required in the device.

A still further object is to provide improved error correction in asemiconductor memory device without increasing chip area.

Another object is to provide improved error detection and correctionmethod circuitry in a DRAM wherein error detection and correction rateis reduced.

A further object is to provide improved error detection and correctionmethod and circuitry in a DRAM formed of single transistor-singlecapacitor type memory cells, wherein error detection and correction rateis reduced.

The semiconductor memory device having an error correcting circuit inaccordance with a first aspect of the present invention comprises amemory cell array having a plurality of memory cells arranged in thematrix fashion comprising rows and columns and each storing information;a plurality of word lines connecting the memory cells arranged in a rowdirection; a plurality of bit line pairs connecting the memory cellsarranged in a column direction and each constituting a return bit line;error detecting means connected to a plurality of bit line pairs fordetecting an error of information of each bit line pair; informationinverting means provided corresponding to respective bit line pairs forinverting information of the corresponding bit line pair; firstswitching means for connecting each bit line pair to each informationinverting means; second switching means for outputting informationinverted by each information inverting means to the corresponding bitline pair; and control means for controlling the first switching meanscorresponding to the bit line pair in response to error detection ofinformation of any bit line pair by error detecting means, controllingthe corresponding second switching means while cutting the correspondingbit line pair from the information inverting means, and outputting theinverted information on the corresponding bit line pair.

As described above, in a semiconductor memory device in accordance withthe present invention, an error correcting circuit can be containedwithout any increase in the number of I/O bus line pairs and, therefore,any error can be detected and corrected at high speed without increasingin chip area.

In a more preferred embodiment, a plurality of bit line pairs comprisebit lines and inverted bit lines. The bit line is connected toinformation inverting means by a first switching transistor and theinverted bit line is connected to the information inverting means by asecond switching transistor. The information inverting means comprisesfirst and second inverting and amplifying means. The first inverting andamplifying means holds and inverts the information applied from the bitline through the first switching transistor and outputs the same ontothe bit line through the second switching means. The second invertingand amplifying means holds and inverts the information inputted from theinverted bit line through the second switching transistor and outputsthe same to the inverted bit line through the second switching means.

The second aspect of the invention is a method for correcting the errorof data in the semiconductor memory device, by which data stored in amemory cell arranged in matrix fashion consisting of rows and columns isread to the bit line pair and as the read data is inverted, the error ofthe data is detected and the inverted data is outputted to the bit linepair in response to detection of the error of the data and the inverteddata is stored into the respective memory cells so that the error of thedata is corrected.

These objects and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram showing the whole structure of aconventional MOS dynamic RAM;

FIG. 2 is a concrete electric circuit diagram of the memory cell arrayshown in FIG. 1;

FIG. 3 is a schematic block diagram showing the whole structure of oneembodiment of the present invention;

FIG. 4 is an electric circuit diagram in a main portion of oneembodiment of the present invention;

FIG. 5 is a concrete electric circuit diagram of the error detectingcircuit shown in FIG. 4;

FIG. 6 is a timing diagram for describing the operation of oneembodiment of the present invention;

FIG. 7 is an electrical circuit diagram in a main portion of anotherembodiment of the present invention; and

FIG. 8 is a timing diagram for describing the operation of theembodiment shown in FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 is a schematic block diagram showing the whole structure of oneembodiment of the present invention.

In this embodiment of the present invention, in addition to theconventional MOS dynamic RAM shown in FIG. 1, an error detecting circuit30, a first switching circuit 50, an inversion amplifier 60, and asecond switching circuit 70 are provided. The error detecting circuit 30detects an error in the data read from the memory cell array 3. Thefirst switching circuit 50 applies the data read from the memory cellarray 3 to the inversion amplifier 60. The inversion amplifier 60inverts the data read from the memory cell array 3 and the secondswitching circuit 70 outputs the data inverted by the inversionamplifier 60 to the memory cell array 3.

Next, the operation will be described. The first switching circuit 50applies the data read from the memory cell array 3 to the inversionamplifier 60 and inverts the same therein. At this time, the secondswitching circuit 70 is non-conductive, so that the data inverted at theinversion amplifier 60 is not applied to the memory cell array. However,when the error detecting circuit 30 detects the error of the data, theerror detecting circuit 30 renders the first switching circuit 50non-conductive and it renders the second switching circuit 70conductive. Therefore, the data inverted at the inversion amplifier 60is applied to the memory cell, array through the second switchingcircuit 70 and thus, the error of the data is corrected.

FIG. 4 is a more detailed electric circuit diagram of the abovedescribed one embodiment of the present invention, and FIG. 5 is anelectric circuit diagram showing one example of the error detectingcircuit shown in FIG. 4.

Referring to FIGS. 4 and 5, a description is made of the structure ofthe illustrated embodiment of the present invention. The semiconductormemory device having the error correcting circuit shown in FIG. 4 isstructured in the same manner as that of the aforementioned FIG. 2,except for the following.

Bit line pairs BL₀ and BL₀ to BL₆₃ and BL₆₃ are connected to inputs ofinverting amplifiers 14 to 17 through N channel MOS transistors 41 to44. These N channel MOS transistors 41 to 44 are turned on at a highvoltage level to connect the bit line pairs BL₀ and BL₀ to BL₆₃ and BL₆₃to the inverting amplifiers 14 to 17 and cut off at a low voltage level.The inverting amplifier 14 comprises N channel MOS transistor 18 and Pchannel MOS transistor 19 and gates of the transistors 18 and 19constitute the input of the inverted amplifier 14 which is connected tothe source of the transistor 42. The transistors 18 and 19 have theirdrains connected together to the source of the transistor 41. A RNsignal is applied to the source of the transistor 18 and a RP signal isapplied to the source of the transistor 19. Similarly, the invertingamplifiers 15, 16 and 17 comprise transistors 20 to 25 and they arestructured in the same manner as that of the inverting amplifier 14.

The N channel MOS transistors 26 and 28 control the conduction betweenthe outputs of the inverting amplifiers 14 and 16 and the inverted bitlines BL₀ and BL₆₃, respectively, and the transistors 27 and 29 controlconduction between the outputs of the inverting amplifiers 15 and 17 andthe bit lines BL₀ and BL₆₃, respectively. For this purpose, the drainsof the transistors 26 and 28 are connected to the transistors 41 and 43,respectively, and the sources of the transistors 26 and 28 are connectedto the inverted bit lines BL₀ and BL₆₃ and to an error detecting circuit30. The sources of the transistors 27 and 29 are connected to the bitlines BL₀ and BL₆₃ and also to the error detecting circuit 30 and thedrains of the transistors 27 and 29 are connected to the sources of thetransistors 42 and 44.

A control circuit 40 is provided in order to control the conduction ofthe above mentioned transistors 41 to 44. The control circuit 40comprises an odd number of inverters 31 to 33 connected in cascade, aNAND gate 34, an inverter 35, and an odd number of inverters 36 and 37connected in cascade. An activation signal SP is applied from a sensesignal generating circuit 7 to the control circuit 40 and a RP signaloutputted from the output of the inverter 31 and a RN signal outputtedfrom the output of the inverter 32 are applied to respective invertingamplifiers 14 to 17. A signal DT is outputted from the output at theinverter 35, which is applied to the gates of the transistors 41 to 44.A control signal is to be applied to the error detecting circuit 30through the inverters 33, 36 and 37 and when the error detecting circuit30 receives the control signal, it applies error detection signals SY₀to SY₆₃ to the gates of the transistors 26 to 29.

Next, referring to FIG. 5, a description is made of a structure of theerror detection circuit 30. The error detection circuit 30 comprises asyndrome generating circuit 301, a register 303, a syndrome decoder 304and AND gates 305. The syndrome generating circuit 301 comprisescombinations of a plurality of exclusive OR circuits 302 and informationread from each memory cell through each bit line pair is applied to thesyndrome generating circuit 301. In the syndrome generating circuit 301shown in FIG. 5, the bit line pair is represented by one line for thesake of clarity of the drawing.

A signal SY_(i) of an element of each row of syndrome generated by thesyndrome generating circuit 301 is stored in the register 303. Thesignal SY_(i) and a complementary signal are generated by the register303 and these signals SY_(i) and SY_(i) are applied to the syndromedecoder 304. The outputs of the syndrome decoder 304 are applied to theAND gates 305 and error detection signals SY₀ to SY₆₃ are outputted fromthe AND gates 305. Since the thus structured error detection circuit 30is known to those skilled in the art, more detailed description isomitted.

FIG. 6 is a timing diagram shown for the illustrated embodiment of thepresent invention.

Referring to FIG. 4 to FIG. 6, a description is made of operation of thedescribed embodiment of the present invention. The timing diagram shownin FIG. 6 represents a case in which when the i-th word line WL_(i) isselected, an error is detected in the j-th bit line pair BL_(j) andBL_(j). A potential of the word line WL_(i) and a dummy word line DW_(k)(k=0, 1) selected by the row decoder 1 is raised as shown in FIG. 6(a)and (b) in response to the row address signal applied from the outsideof the chip and an electric charge representing information of a memorycell is read on each bit line pair and, as a result, a potential changeis generated as shown in FIG. 6(c).

Then, the sense signal generating circuit 7 outputs a low level signalSN as shown in FIG. 6(d) and a high level signal SP as shown in FIG.6(e). In response to these signals, the sense amplifier SA is activatedand a voltage on the bit line pair is amplified.

On the other hand, the signal SP is delayed by the inverters 31 to 33and inverting amplifiers 14 to 17 are activated by a signal RP shown inFIG. 6(g) which is outputted from the inverter 31 and by a signal RNshown in FIG. 6(h) which is outputted from the inverter 32. In addition,the signal SP and the delayed signal SP are applied to NAND gate 34 tobe pulse-shaped and the pulse output is inverted by the inverter 35,with the result that a signal DT as shown in FIG. 6(f) is applied to thetransistors 41 to 44. As a result, the transistors 41 to 44 are turnedon and information of the bit line pairs BL₀ and BL₀ to BL₆₃ and BL₆₃ istransferred to the inverting amplifiers 14 to 17, with the result that apotential state is decided.

Then, a potential of the signal DT becomes a low level and thetransistors 41 to 44 are turned off and, as a result, the bit line pairsBL₀ and BL₀ to BL₆₃ and BL₆₃ are electrically separated from theinverting amplifiers 14 to 17. Thereafter, the error detection circuit30 inspects the data of each bit line pair and if an error is detectedin the 0-th bit line pair BL₀ and BL₀, for example, it generates asignal SY₀ and renders the transistors 26 and 27 conductive. When thetransistors 26 and 27 are turned on, the output of the invertingamplifier 15 for inverting the information of the bit line BL₀ isoutputted on the bit line BL₀ through the transistor 27 and the outputof the inverting amplifier 14 for inverting the information of theinverted bit line BL₀ is outputted on the inverted bit line BL₀ throughthe transistor 26. As a result, the respective information of the bitline pair BL₀ and BL₀ is inverted.

FIG. 7 is a detailed block diagram showing another embodiment of thepresent invention.

In the embodiment shown in FIG. 7, bit line pairs BL₀ and BL₀ to BL₆₃and BL₆₃ are separated from sense amplifiers SA₀ to SA₆₃ prior to theinversion of a potential of the bit line pair on which an error has beendetected, and respective bit line pairs BL₀ and BL₀ to BL₆₃ and BL₆₃ areshort-circuited so as to be made equal in potential, with the resultthat potentials of the bit line pairs BL₀ and BL₀ to BL₆₃ and BL₆₃ areinverted at high speed. For this purpose, N channel MOS transistors 51to 54 are inserted between the sense amplifiers SA₀ to SA₆₃, and the bitline pairs BL₀ and BL₀ to BL₆₃ and BL₆₃ to which each of memory cellsMC₀, ₀ to MC₆₃, ₆₃ and dummy cells DM₀, ₀ to DM₆₃, ₁ are connected and asignal TG is applied to the gates of the transistors 51 to 54. Althoughthe signal TG is usually at a high level and the transistors 51 to 54are on, the signal TG becomes a low level to separate the senseamplifiers SA₀ to SA₆₃ from each of memory cells MC₀, ₀ to MC₆₃, ₆₃ anddummy cells DM₀, ₀ to DM₆₃, ₁, when an error in the information of thebit line pairs BL₀ and BL₀ to BL₆₃ and BL₆₃ is detected. The signal RNis delayed by inverters 45 and 46, whereby the signal TG is created asshown in FIG. 8(j).

In addition, N channel MOS transistors 55 and 56 are connected in orderto short-circuit between each of bit line pairs BL₀ and BL₀ and BL₆₃ andBL₆₃ respectively. A signal EQ is applied to each gate of thetransistors 55 and 56. Although the signal DT is delayed by inverters 47and 48, whereby the signal EQ is created as shown in FIG. 8(k) and it isusually at a low level, the signal becomes low level to turn thetransistors 55 and 56 on and to short-circuit between each of bit linepairs BL₀ and BL₀ and BL₆₃ and BL₆₃, respectively, when an error ofinformation is detected.

Therefore, when an error of information is detected, the senseamplifiers SA₀ to SA₆₃ are separated from each of memory cells MC₀, ₀ toMC₆₃, ₆₃ and dummy cells DM₀, ₀ to DM₆₃, ₁ to short-circuit each of bitline pairs BL₀ and BL₀ to BL₆₃ and BL₆₃ and, as a result, a potential ofeach of bit line pairs BL₀ and BL₀ to BL₆₃ and BL₆₃ can be inverted athigh speed.

More specifically, in the above mentioned embodiment shown in FIG. 4,when a potential of the bit lines BL₀ and BL₀ are inverted by theoutputs of the inversion amplifiers 14 and 15, it took a relatively longtime until the potentials of the bit line BL₀ and the inverted bit lineBL₀ were inverted because the potential before inversion and thepotential after inversion are overlapped as shown in FIG. 6(c).

Meanwhile, in this embodiment, when the signal TG becomes a low level,the transistors 51 and 52 become non-conductive as shown in FIG. 8(j)and the sense amplifier SA₀ to SA₆₃ are separated from each of memorycells MC₀, ₀ to MC₆₃, ₆₃ and dummy cells DM₀, ₀ to DM₆₃, ₁. Thereafter,as shown in FIG. 8(k), when the signal EQ becomes high level a fewmilliseconds later, the transistors 55 and 56 become conductive to shortcircuit between the bit line pairs BL₀, BL₀ to BL₆₃, BL₆₃. Therefore,the potential of each of bit line pairs BL₀, BL₀ to BL₆₃, BL₆₃ becomes 0steeply and, thereafter, when the potential of a signal SY_(j) shown inFIG. 8(i) becomes high, the potentials of the bit line pairs BL₀, BL₀ toBL₆₃, BL₆₃ are inverted. Consequently, the potentials of the bit linepairs BL₀, BL₀ to BL₆₃, BL₆₃ can be inverted at high speed as comparedwith the embodiment shown in FIG. 4.

Although the signals RP and RN are shown as being applied to each sourceof the transistors 18 to 25 contained in the inverting amplifiers 14 to17, it is to be understood that the present invention is not limited tothis and fixed potentials such as a power supply potential and theground potential may be applied.

Therefore, according to the present invention, since each bit line pairis separated from the corresponding information inverting means inresponse to error detection of the information of any bit line pair, andthe inverted information by the information inverting means is outputtedon the corresponding bit line pair, whereby the information of the bitline pair is forcedly rewritten, an error correcting circuit can becontained in a semiconductor memory without any increase in the numberof I/O bus line pairs and, therefore, an error can be detected andcorrected at high speed while an increase in chip area can be controlledas much as possible.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. A semiconductor memory device having an errorcorrecting circuit, comprising:a memory cell array having a plurality ofmemory cells arranged in a matrix comprising rows and columns of eachstoring information; a plurality of word lines connected said memorycells arranged in a row direction; a plurality of bit line pairsconnecting said memory cells arranged in a column direction, each ofsaid bit line pairs constituting a return bit line; error detectingmeans connected to a plurality of bit line pairs for detecting an errorof information of each bit line pair; information inverting meansprovided corresponding to respective bit line pairs for invertinginformation of the corresponding bit line pair; first switching meansfor connecting each said bit line pair to each said informationinverting means; second switching means for outputting informationinverted by each said information inverting means to the correspondingbit line pair; and control means for controlling the first switchingmeans corresponding to the bit line pair in response to detection of anerror of information of any bit line pair by error detecting means,controlling the corresponding second switching means while cutting thecorresponding bit line pair from the information inverting means, andoutputting the inverted information on the corresponding bit line pairwhereby the detected error of information is corrected.
 2. Asemiconductor memory device having an error correcting circuit inaccordance with claim 1, wherein said plurality of bit line pairs eachcomprise a bit line and an inverted bit line andwherein said firstswitching means comprises: a first switching transistor for connectingsaid bit line to said information inverting means; and second switchingtransistor for connecting said inverted bit line to said informationinverting means.
 3. A semiconductor memory device having an errorcorrecting circuit in accordance with claim 2, wherein said informationinverting means comprises:first inverting amplifying means having itsinput connected to said bit line through said first switching transistorand its output connected to said bit line through said second switchingmeans for holding and inverting the inputted information; and secondinverting amplifying means having its input connected to said invertedbit line through said second switching transistor and its outputconnected to said inverted bit line through said second switching meansfor holding and inverting the inputted information.
 4. A semiconductormemory device having an error correcting circuit in accordance withclaim 3, wherein said second switching means comprises:a third switchingtransistor connected between the input of said first invertingamplifying means, the output of said second inverting amplifying meansand said inverted bit line for applying the output of said secondinverting amplifying means to said inverted bit line in response toerror detection of information by said error correcting and detectingmeans; and a fourth switching transistor connected between the output ofsaid first inverting amplifying means, the input of said secondinverting amplifying means and said bit line for applying the output ofsaid first inverting amplitude means to said bit line in response toerror detection of information by said error correcting and detectingmeans.
 5. A semiconductor memory device having an error correctingcircuit in accordance with claim 2 further comprising:a sense amplifierto which information of said bit line and said inverted bit line areapplied; a fifth switching transistor for connecting said bit line tosaid sense amplifier; a sixth switching transistor for connecting saidinverted bit line to said sense amplifier; a seventh switchingtransistor for short-circuiting said bit line and said inverted bitline; means for turning said fifth and sixth switching transistors offin response to error detection of said information by said errorcorrecting and detecting means, turning said seventh switchingtransistor on after separating said bit line and said inverted bit linefrom said sense amplifier, and short-circuiting said bit line and saidinverted bit line to make respective bit lines equal in potential.
 6. Asemiconductor memory device having an error correction circuit inaccordance with claim 2, further comprising:a row decoder connected toeach said word line for selecting any word line; an input/output linefor outputting information of each said bit line and each said invertedbit line to the outside and applying information from the outside tosaid each bit line and said each inverted bit line; a eighth switchingtransistor for connecting said input/output line to said bit line andsaid inverted bit line; and a column decoder for selecting any one ofsaid eighth switching transistor and connecting the corresponding bitline and inverted bit line to said input/output line.
 7. In asemiconductor memory device comprising a memory cell array arranged in amatrix including rows and columns and word lines and bit line pairs, amethod for correcting an error in information read from said memory cellarray comprising the steps of:reading information stored in said memorycell array onto said bit line pairs in response to a signal applied tosaid word lines; simultaneously inverting the information read on saidbit line pairs and detecting an error in the information read on saidbit line pairs; and selectively applying said inverted information ontosaid bit line pairs in response to said detection of an error in theinformation thus correcting an error in the information.
 8. In asemiconductor memory device comprising a memory cell array arranged in amatrix including rows and columns, sense amplifiers, word lines and bitline pairs, a method for correcting an error in information read fromsaid memory cell array comprising the steps of:reading the informationstored in said memory cell array onto said bit line pairs in response toa signal applied to said word lines; simultaneously inverting theinformation read onto said bit line pairs and detecting an error in theinformation read onto said bit line pairs; disconnecting said senseamplifiers from said bit line pairs; equalizing said bit line pairs byshort circuiting response bit lines of said bit line pairs to eachother; and outputting said inverted information onto said bit line pairscorrecting an error in the information in response to said detection ofan error in the information and after said bit line pairs aredisconnected from said sense amplifiers and said bit line pairs areequalized.